1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip packaging, and more particularly, to an IC chip package having an IC chip with an overhang and/or ball grid array (BGA) blocking underfill material flow, and related methods.
2. Background Art
Package-on-package (PoP) is a new three-dimensional integrated circuit (IC) chip packaging technology that allows vertical integration of memory and logic ball grid array (BGA) modules. That is, a memory chip package and a logic chip package are stacked on top of one another to form an integrated package with a standard interface to route signals between them. PoP technology is of particular interest to the mobile market, e.g., for cell phones, personal digital assistants (PDAs), camcorders, etc., because it provides for higher density of circuitry.
One challenge with PoP technology is controlling underfill material flow within the integrated package. Underfill material is designed to flow well to encase controlled collapse chip connectors (C4) under the chip, and typically requires approximately 2.5 millimeter (mm) of space around an IC chip. If such a space is not available (e.g., due to BGA pad locations), the underfill material needs to be stopped by other measures. This issue arises relative to PoP technology when, for example, the bottom package includes a flip chip plastic ball grid array (FC-PBGA). In this situation, as shown in FIG. 1, a top package 10 must be assembled to BGA pads 12 that are on a top surface 14 of a laminate 16 of a bottom package 18. Due to tight space constraints, as shown in left enlarged area in FIG. 1, underfill material 20 oftentimes can flow too far and contaminate, or even cover, BGA pads 12 and prevent joining of top package 10 to bottom package 18. As shown in FIG. 2, one current approach to this problem includes using a dam of ink 22 that is dispensed around IC chip 24 of bottom package 18 to stop underfill material 20 flow. This approach, however, presents a number of disadvantages such as increased cycle time and costs, additional equipment requirements, etc.
Another challenge related to controlling underfill material is maintaining the integrated chip package height very small. In this case, as shown in the right enlarged area in FIG. 1, limiting of underfill material 20 bleed on top of IC chip 24 of bottom package 18 is imperative since there is very limited space (S) between the bottom package's top surface 26 and a bottom surface 28 of top package 10. Currently, it is very difficult to underfill a thin chip while limiting the underfill material bleed on the chip packages' top surface to very small margins.